Using Serial Peripheral Interface (SPI) Master and Slave with Atmel AVR Microcontroller. Sometimes we need to extend or add more I/O ports to our microcontroller based project. Because usually we only have a limited I/O port left than the logical choice is to use the serial data transfer method; which usually only requires from one up to four ports for doing the data transfer. Currently there are few types of modern embedded system serial data transfer interface widely supported by most of the chip’s manufactures such as I2. C (read as I square C), SPI (Serial Peripheral Interface), 1- Wire (One Wire), Controller Area Network (CAN), USB (Universal Serial Bus) and the RS- 2. RS- 4. 23, RS- 4. RS- 4. 85). The last three interface types is used for long connection between the microcontroller and the devices, up to 1.
Interfacing with Hardware. These topics cover the hardware and software setup required to connect an Arduino device with a variety of electronic parts, chips and devices.
RS- 4. 85 specification, while the first three is used for short range connection. Among these serial data transfer interface types, SPI is considered the fastest synchronous with full duplex serial data transfer interface and can be clocked up to 1. MHz; that is why it is widely used as the interface method to the high speed demand peripheral such as the Microchip Ethernet controller ENC2. J6. 0, Multi Media Card (MMC) Flash Memory, Microchip SPI I/O MCP2. S1. 7, Microchip 1. K SPI EEPROM 2. 5AA1.
ADC, sensors, etc. In this tutorial we will learn how to utilize the Atmel AVR ATMega. SPI peripheral to expand the ATMega.
I/O ports and to communicate between two microcontrollers with the SPI peripheral where one microcontroller is configured as a master and other as a slave. The principal we learn here could be applied to other types of microcontroller families. Serial Peripheral Interface (SPI)The standard Serial Peripheral Interface uses a minimum of three line ports for communicating with a single SPI device (SPI slave), with the chip select pin (CS) is being always connected to the ground (enable). If more the one SPI devices is connected to the same bus, then we need four ports and use the fourth port (SS pin on the ATMega. SPI device before starting to communicate with it. If more then three SPI slave devices, then it is better to use from three to eight channels decoder chip such as 7. HC1. 38 families.
Since the SPI protocol uses full duplex synchronous serial data transfer method, it could transfer the data and at the same time receiving the slave data using its internal shift register. From the SPI master and slave interconnection diagram above you could see that the SPI peripheral use the shift register to transfer and receive the data, for example the master want to transfer 0b. E) to the slave and at the same time the slave device also want to transfer the 0b. By activating the CS (chip select) pin on the slave device, now the slave is ready to receive the data. On the first clock cycle both master and slave shift register will shift their registers content one bit to the left; the SPI slave will receive the first bit from the master on its LSB register while at he same time the SPI master will receive its first data from slave on its LSB register. Continuously using the same principal for each bit, the complete data transfer between master and slave will be done in 8 clock cycle. By using the highest possible clock allowed such as the Microchip MCP2.
S1. 7 SPI slave I/O device (1. MHz) than the complete data transfer between the microcontroller and this SPI I/O port could be achieve in 0. As you understand how the SPI principal works, now its time to implement it with the Atmel AVR ATMega. The following is the list of hardware and software used in this project: 7. HC5. 95, 8- bit shift registers with output latch.
Microchip MCP2. 3S1. SPI I/O Expander. Resistor: 3. 30 Ohm (8), 1. K (1)Eight 3 mm blue LEDOne micro switch. AVRJazz Mega. 16. AVR ATmega. 16. 8 microcontroller (board schema). Win. AVR for the GNU’s C compiler.
Atmel AVR Studio 4 for the coding and debugging environment. STK5. 00 programmer from AVR Studio 4, using the AVRJazz Mega.
STK5. 00 v. 2. 0 bootloader facility. Expanding Output Port with 7. HC5. 95 8- bit Shift Registers. Because the basic operation of SPI peripheral is a shift register, then we could simply use the 8- bit shift register with output latch to expand the output port.
The 1. 6 pins 7. 4HC5. The 7. 4HC5. 95 device has 8- bit serial- in, parallel- out shift register that feeds directly to the 8- bit D- type storage register. The 8- bit serial- in shift register has its own input clock pin named SCK, while the D- Latch 8- bit registers use pin named RCK for transferring (latching) the 8- bit shift registers output to D- Latch output registers. In normal operation according to the truth table above the 7. HC5. 95 shift registers clear pin (SCLR) should be put on logical high and the 8- bit D- Latch buffer output enable pin (G) should be put on logical low. By feeding the serial input pin (SER) with AVR ATMega.
MOSI) and connecting the master synchronous clock (SCK) to the 7. HC5. 95 shift registers clock (SCK), we could simply use the 7.
HC5. 95 as the SPI slave device. Optionally we could connect the 7. HC5. 95 Q’H output pin (shift registers MSB bit) to the master in slave out pin (MISO); this optional connection will simply returns the previous value of the shift registers to the SPI master register. Now let’s take a look to the C code for sending simple chaser LED display to the 7.
HC5. 95 output: /*****************************************************************************. File Name : avrspi. Version : 1. 0. Description : SPI I/O Using 7. HC5. 95 8- bit shift registers. Author : RWB. // Target : AVRJazz Mega.
Board. // Compiler : AVR- GCC 4. Win. AVR 2. 00. 80. IDE : Atmel AVR Studio 4. Programmer : AVRJazz Mega. STK5. 00 v. 2. 0 Bootloader.
AVR Visual Studio 4. STK5. 00 programmer. Last Updated : 2. May 2. 00. 9. *****************************************************************************/. SPI. To initialize the SPI peripheral inside the ATMega. SPI master and set the master clock frequency using the SPI control register (SPCR) and SPI status register (SPST), for more information please refer to the AVR ATMega. The Swamp Thing V1 V2 V3 V4 St.
The first thing before we use the SPI peripheral is to set the SPI port for SPI master operation; MOSI (PB3) and SCK (PB5) as output port and MISO (PB4) is the input port, while the SS can be any port for SPI master operation but on this tutorial we will use the PB2 to select the SPI slave device. The following C code is used to set these SPI ports.#define SPI. For all other bits we just use its default value (logical “0“); such as the data order (DORD) bit for first transferring MSB, using the rising clock for the master clock on clock polarity (CPOL) bit and sampled the data on leading edge clock phase (CPHA) bit. Because the 7. 4HC5. Mhz clock rate, then I use the fastest clock that can be generated by the ATMega.
SPI peripheral which is fsc/2 (the AVRJazz Mega. MHz); therefore the maximum clock generated by the SPI master will be 5.
MHz. This frequency can be achieved by setting the SPR1=0 and SPR0=0 in the SPCR register and SPI2. X=1 in the SPSR register.// Enable SPI, Master, set clock rate fck/2 (maximum). SPCR = (1< < SPE). Each of the MCP2. S1. 7 general I/O pins could be configured to generate interrupt when the ports pin changes its state (for more information please refers to Microchip MCP2. S1. 7 datasheet).
For the purpose of this tutorial we will use the Microchip MCP2. S1. 7 just as the ordinary input and output expander for the AVR ATMega. The MCP2. 3S1. 7 is configured to use address 0x. A0,A1 and A2 are connected to the ground) and the push button switch connected to GPB0 port will be use as the toggle button to start and stop the chaser LED display attached to the GPA0 to GPA7 ports. The following is the C code to achieve these tasks./*****************************************************************************. File Name : mcp.
Version : 1. 0. Description : SPI I/O Using Microchip MCP2. S1. 7 1. 6- Bit I/O Expander. Author : RWB. // Target : AVRJazz Mega. Adobe Animal Clinic Scottsdale Az Restaurants. Board. // Compiler : AVR- GCC 4. Win. AVR 2. 00. 80.
IDE : Atmel AVR Studio 4. Programmer : AVRJazz Mega. STK5. 00 v. 2. 0 Bootloader. AVR Visual Studio 4. STK5. 00 programmer. Last Updated : 2.
May 2. 00. 9*****************************************************************************/. SPI. First the SPI master has to send the MCP2. S1. 7 SPI slave ID with its physical address (set by A2, A1 and A0 pins) and the read or write instruction to the MCP2. S1. 7. Secondly the SPI master has to tell MCP2. S1. 7 which one of the MCP2. S1. 7 control registers address we want to use, and the last one we send or read the actual data.
From the MCP2. 3S1. SPI addressing diagram above you could see that at least we need to perform three SPI master writing to send or read the data to or from the MCP2.
S1. 7 SPI slave I/O expander. Using the same principal we’ve learned from the 7. HC5. 95 to send the data we simply supply the correct data to the ATMega. SPDR register while keep the SS (PB2) pin low to enable the MCP2. S1. 7 SPI slave device.
After all data has been sent or read then we raise (logical “1“) the SS (PB2) pin to deactivate the SPI slave device. The SPI. As you’ve seen from the SPI. The default power- up condition of MCP2.
S1. 7 is all I/O ports configured as an input port. By changing each of the I/O direction registers (IODIRA and IODIRB) we could change this port behavior; this pretty much the same as we set the data direction register on the ATMega. I/O ports. The following code shows how to initialize the MCP2. S1. 7 SPI I/O expander.// Initial the MCP2. S1. 7 SPI I/O Expander. SPI. Remember this setup is different compare to the ATMega.
FF for output and 0x. To make sure all the GPIOB input ports are on known state (all ports high), we activate the MCP2. S1. 7 pull- up resistors by assigning 0x.
FF to the GPPUB register. To enable the MCP2. S1. 7 addressing mode, we have to enable (logical “1“) the HAEN bit on the IOCONA register.